V. Divyapraba ¹, K. Kishore Kumar ¹, R. Pratheepa ¹, V. Elamaran ¹

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Spectrum sensing is the major tasks of cognitive radio for utilizing spectrum resources efficiently thereby identifying and making use of spectrum holes is the objective of sensing. Energy detection technique is adopted to compare the performance of different modulated signals in poor and good SNR. Probability of detection and false alarm are the metrics used to identify the number of primary users over a bandwidth of 5MHz. False alarm is kept constant to increase the detection probability. Simulink model for detections based on FFT and Welch periodogram are implemented. Modulated signals having high data rates can occupy more number of users thereby increasing the usage of spectrum. Also increase in noise should not affect the detection of primary users and reduce the probability of misdetection. Receiver operating characteristic curve is used to analyze the detections with respect to false alarm probability for different ranges of SNR. Noise uncertainty and SNR wall which can limit the performances are also taken into consideration. A unique approach to energy detection based on FFT shows increase in the sensing in the form of spectrum estimation with four primary users and the noise is assumed to be additive white Gaussian. Neyman Pearson hypothesis is considered for determining the presence and absence of users. Noise is the factor which decreases the performance of energy detector in case of blind sensing which can be limited with the help of highly modulated signals. The growing demand for spectrum makes cognitive radio an important technology to be focused in which the sensing process can reduce the interference caused to the primary users.

Keywords

Energy Detection, FFT, Modulation Techniques, Spectrum Sensing, Welch Periodogram

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V. Nandhini ¹, R. Pratheepa ¹, N. Anjana ¹, V. Elamaran ¹

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavaur – 613401, Tamil Nadu, IN

Abstract

In the field of image processing, contrast enhancement is a vital area to enhance contrast of images which are having poor contrast. Histogram Equalization (HE) is the method used to increase contrast in images. To improve contrast in images several HE methods persist. By determining the Probability Density Function (PDF) and Cumulative Density Function (CDF), HE expands the distribution of pixels. The overall brightness would be altered while the histogram equalization is being applied is a one kind of disadvantage. The drawback which is mentioned here can be avoided by, classifying the image based on intensity exposure and is divided into sub images based on the median value. To minimize the over enhancement, the sub images are clipped using the threshold value. Equalization can be done separately for each sub images, and the equalized sub images are combined to form a single image. Thus, to keep the brightness and to bring limitation in enhancement rate the classification and subdivision based HE method was proposed which equalizes the image. For color images, this method of equalization performs better than gray scale images. The simulation results for several test images are obtained using Matlab software tool. The results show that the entropy of the proposed method is compared with the standard HE method and it determines the amount of information available in the image. The proposed method provides better enhancement than other methods of equalization by controlling the enhancement rate. Improvements can be done by selecting the threshold values for clipping and intensity exposure. Contrast enhancement is applied in the areas of photography, medical imaging and video surveillance systems to enhance quality in images and the image looks natural.

Keywords

Classifcation, Clipping, Contrast Enhancement, Entropy, Exposure, Histogram Equalization

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N. Anjana ¹, J. Jezebel Priestley ¹, V. Nandhini ¹, V. Elamaran ¹

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavaur – 613401, Tamil Nadu, IN

Abstract

Image enhancement is one of the major research areas in the field of digital image processing. The sole objective of this domain is to enhance the quality of a poor contrast image. As a result, the final processed image becomes much more understandable than the original one. A new edge based histogram equalization method is proposed in this study. A high pass filter is used to detect edges with a help of an appropriate gradient operator. In general, a convolution mask is used for this kind of area processes like filtering. This proposed method increases the quality of the poor contrast area. This method does not create an impact on brighter area in the given input image. A few portion of the poor contrast is raised and few others contrast are being reduced. The simulation results of this study are compared with the conventional histogram equalization. Our experimental results show that the Peak Signal-to-Noise Ratio (PSNR) is better than the regular Histogram Equalization (HE) method. All simulation results are obtained using Matlab simulation software tool with standard color test images. Color image enhancement methods are applicable in the areas such as iris recognition, digital photography, remote sensing, biology, medicine, geophysics and microarray techniques, etc.

Keywords

Contrast Enhancement, Edge Detection, Histogram Equalization, Image Enhancement, PSNR

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Thadigotla Venkata Subbareddy ¹, Chakka Sri Harsha Kaushik ¹, Har Narayan Upadhyay ¹, V. Elamaran ¹

Affiliations
1 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm² layout area, which is less compared with 765.5 μm² produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

Keywords

CMOS, FPGA, Look-Up Table, Microwind, PROM, Pseudo-nMOS.

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S. Anusha ¹, T. R. Shanmugapriya ¹, S. Venkatalakshmi ¹, Har Narayan Upadhyay ², V. Elamaran ²

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.

Keywords

Altera FPGA, Carry Look-Ahead Adders, High Speed Adders, Reduced Full Adder, VLSI.

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Thadigotla Venkata Subbareddy ¹, Saureddy Omkar Reddy ¹, Chakka Sri Harsha Kaushik ¹, V. Elamaran ¹

Affiliations
1 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613 401, Tamil Nadu, IN

Abstract

Adaptive filters are playing a vital role in signal processing and communication filed of engineering for the purpose of filtering the unwanted signal, signal denoising, signal enhancement, etc. The main characteristic of the adaptive filter is the adjustment of filter coefficients dynamically with respect to the input signal which helps a lot in signal processing applications. This study main focus on implementing such adaptive filters on digital signal processors. The adaptive filtering algorithms such as Least Mean Square (LMS) algorithm and Normalized LMS (NLMS) algorithms are implemented with TMS320C6713 floating-point DSP processor using LabVIEW environment in real time. To test the functionality of the algorithms, the sinusoid signal is added with noisy and applied as an input the filter and the resultant denoising output is obtained with both the algorithms. We implement it with TMS320C6713 floating-point Digital Signal Processor using LabVIEW environment in real time. Our objective is to reduce or filter the noise using these algorithms and obtain the performance metrics like peak output, Mean Square Error (MSE), Peak Signal-to-Noise Ratio (PSNR) as a part of simulation results. The PSNR produced by the NLMS algorithm is obtained as 18.414 is very high as compared with 3.28416 produced by the LMS algorithm. Interfacing the TMS320C6713 DSP board with the LabVIEW application is done using the Code Composer Studio software tool. This study focuses the principle of adaptive filters by implementing the Least Mean Square (LMS) algorithm and Normalized LMS algorithms and can be further extended with Kalman filters too. er .

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R. Pradhisha ¹, N. Iswarya ¹, K. L. V. Gopinath Reddy ¹, Har Narayan Upadhyay ¹, V. Elamaran ¹

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

This study presents self-checking designs for arithmetic and logic circuits using Field Programmable Gate Array (FPGA) design. At present, we are implementing every circuit using VLSI technology because of its excellent features like low power, less area, wide implementation. Since finding error manually is a tedious process, self-checking method would be most wanted. Self-checking circuits are preferable to Automatic Testing Equipment (ATE) because they demand less hardware, low cost and takes very less test application time. The replica construction and pattern recognition are the two methods presented for self-checking logic gates. Self-checking single-bit full adder, 4-bit adder and 2-bit multiplier circuits are implemented and tested on EP2C20F484C7 Altera Cyclone-II FPGA device using Very High-Speed Integrated Circuits Hardware Description Language (VHDL) script. The test data input samples are applied through input switches and the Error/No Error results are obtained on the 7-segment display device. This study discuss in detail about basic self-checking methods with a experimental way. If the complexity of the circuit increases, the components used and the number of connections between the components increases. As a result, the probability of error occurrence increases for complex designs. But this error occurrence can be avoided to the maximum by using self-checking circuits at different build stages in the complex circuit model. The reliability of any system becomes very important especially in the area of applications such space technology, medical image analysis, military communications, etc.

Keywords

Adders, FPGA, Multipliers, Reliability, Self-Checking, Self-Testing.

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